AR# 33227
|Virtex-6 GTX FPGA Transceiver - Special considerations for RX Buffer Bypass
描述
Bypassing the receive buffer in the Virtex-6 GTX FPGA is an advanced feature and is not supported in all situations. This Answer Record discusses the limitations in bypassing the receive buffer across temperatures and the conditions it can be used reliably.解决方案
;To bypass the receive buffer, the internal parallel clock and the externally provided RXUSRCLK need to be aligned through the Phase Alignment process. This provides a mechanism to modify the phase of the internal clock so that it matches RXUSRCLK with enough accuracy to avoid cross-clock domain setup and hold errors internal to the GTX. In this way, the buffer is no longer required to compensate between the two domains.
An issue arises as temperature changes after phase alignment has been completed. RXUSRCLK is piped through a large amount of the FPGA fabric, and is therefore affected by changes in the speed of the silicon over variations in temperature and voltage. These changes can lead to differences in the delay of RXUSRCLK between it's source and the GTX, resulting in an effective change in phase. Since the internal parallel clock does not see the same change in delay, a large enough phase difference on RXUSRCLK can cause timing errors internal to the GTX.
The RX Delay Aligner that is intended to compensate for this phase change is not supported for General ES. To prevent errors, the temperature variation should be kept within+/-15C after the Phase Alignment process. If the junction temperature exceeds these limits, the phase alignment process will need to be redone.
In addition, the following changes should be made to the phase alignment process in the user application to disable the RX Delay Aligner:
POWER_SAVE[5] = 1
RXDLYALIGNDISABLE = 1
RXDLYALIGNRESET = 0
The following timing diagram demonstrates the usemodel for the phase alignment process:
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| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 33475 | Virtex-6 FPGA GTX Transceiver - Known Issues and Answer Record List | N/A | N/A |