2. 技术支持
  3. AR# 3329: ngd2vhdl M1.3/M1.4: Why does ngd2vhdl create a data type called std_logic_vector2?
  4. AR# 33292: 11.2 Timing Analyzer - Spartan-6 FPGA - Timing Analyzer reports large clock skew between LX25 and LX45

AR# 33292

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11.2 Timing Analyzer - Spartan-6 FPGA - Timing Analyzer reports large clock skew between LX25 and LX45

描述

When I run timing analysis on my Spartan6 FPGA design, I see clock skew which is larger than expected. I also compared LX25 to LX45 and the clock skew did not correlate to the size as expected. When is this going to be fixed?

解决方案

The issue is scheduled to be fixed in the 11.3 release of the software tools.

AR# 33292
日期 12/15/2012
状态 Active
Type 综合文章
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