At higher line rates, the dedicated CHBONDO to CHBONDI paths between the GTP_DUALs have been seen to fail timing.
This Answer Record discusses how to work around this issue.
Because these paths are dedicated in the Spartan-6 architecture, there is no impact to timing from routing and the path has a fixed delay.
The CHBONDO to CHBONDI paths have been verified to work correctly at all supported line rates, and the timing failure reported by the tools is incorrect.
To work around the timing error, apply a TIG constraint to the nets connecting these ports.
This error will be corrected in the 11.4 release of the tools. Please refer to the Constraints Guide (UG625) for more information on how to apply this constraint.
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 33475 | Virtex-6 FPGA GTX Transceiver - Known Issues and Answer Record List | N/A | N/A |
| 33302 | LogiCORE IP XAUI v9.1 and v9.1 rev1 - Release Notes and Known Issues for ISE Design Suite 11.3 and 11.5 | N/A | N/A |
| AR# 33504 | |
|---|---|
| 日期 | 06/22/2017 |
| 状态 | Active |
| Type | 综合文章 |
| 器件 | |