How is the reset implemented in the ChipScope IBERT Core?
Note: This Answer Record is a part of the Xilinx ChipScope Solution Center (Xilinx Answer 45310). The Xilinx ChipScope Solution Center is available to address all questions related to the ChipScope tool. Whether you are starting a new design with the ChipScope tool or troubleshooting a problem, use the ChipScope Solution Center to guide you to the right information.
The reset in the IBERT core is implemented differently depending on the device family that is being used. A description of how the reset is implemented for each device family is listed below.
7 Series Device Family
The reset is implemented as a hardware state machine. The highest level resets are asserted first (for instance,GTXRESET). Any MMCMs in the design will be held in reset while the PLL in the GT is locking. Once RESETDONE is released, the logic in the IBERT core and error counters are reset.
Virtex-6 Family and Spartan-6 Family
This reset is implemented in the same way as the 7 Series reset.
Virtex-5 Device Family
The resets are driven by software with a sequence similar to Virtex-6, Spartan-6 and 7 Series, but the resets are triggered through register accesses to the core. In general, this is a less reliable method of resetting the transceivers, which is why the change was made in the newer device families.
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 45310 | Xilinx ChipScope Solution Center | N/A | N/A |