The Virtex-6 FPGA GTX Transceiver User's Guide (UG366) indicates that if any transceivers are going to be used in the device, the first quad to be utilized should be QUAD_115. This is due to the resistor calibration being located in GTX0 in QUAD_115. If a design has been implemented that does not utilize this GTX in this quad, the calibration information will not be propagated correctly to the transceivers that are being used and could lead to data errors. This answer record discusses how to implement a dummy instance at QUAD_115 to ensure that the resistor calibration circuit is enabled correctly.
It is not yet mentioned in UG366 that it specifically has to be GTX0 that is instantiated in QUAD_115. This is to be added in a future update to the user guide.
The Virtex-6 GTX Transceiver Wizard allows the user to select both "No TX" and "No RX" to generate an instantiation that disables and powers down both the TX and RX sides of the transceiver. The wrapper generated only has 4 ports; 2 for the differential TX pins and 2 for the differential RX pins. These need to be routed to the top level of the design as inputs (RX) and outputs (TX) to keep the transceiver from being optimized out of the design.
To ensure that the GTX Transceiver is locked down correctly on GTX0 in QUAD_115 for designs in 11.x, please see the Virtex-6 FPGA GTX Transceiver User's Guide (UG366) for package placement information and use of a transceiver in QUAD_115.
In 12.1 and later, the auto macro instantiation does this automatically, see (Xilinx Answer 35055).
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 33475 | Virtex-6 FPGA GTX Transceiver - Known Issues and Answer Record List | N/A | N/A |