AR# 34420

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Virtex-6 GTX SIS Kit Known Issues

描述

This article contains a list of Known Issues for Virtex-6 FPGA HSSIO electrical simulation models.

解决方案

HSPICE
V1.1
Windows version of HSPICE v2009.09 has a problem with the .hdl card using environment variables. The path could be changed to a relative path (commented line).

V1.0
In files v6_gtx_oma_5ones_5zeroes.ckt, v6_gtx_pulse.ckt and v6_gtx_step.ckt, update the pattern statement to correctly reflect the width of the UI.
Windows version of HSPICE v2009.03-SP1 has a problem with the .hdl card using environment variables. The path could be changed to a relative path (commented line)

Windows
HSPICE v 2008.09 does not work with this kit at all.
HSPICE v 2009.03 works (tested version). This also works with mixed model simulation.
HSPICE v 2010.03 does not work in a mixed module simulation (i.e. Virtex-6 transmitter - Virtex-5 receiver).
HSPICE v 2010.03 could crash right after the License Check. No Licensefile is written. Please update to HSPICE v 2010.03 SP2.
HSPICE v 2010.03 SP2 does not work in a mixed module simulation (i.e.Virtex-6 transmitter - Virtex-5 receiver).

Linux
HSPICE v2009.03 works.
HSPICE v2009.03-SP1 not tested (unavailable in farm).
HSPICE v2009.06 works.

ELDO
(updated February 22nd 2010)
V1.0
To enable better DC convergence, in the HyperLynx Installation directory, in the bsw.ini file, set ForceFixedStep=0 under the [SPICE] keyword. Please ensure that HyperLynx is closed before making the change, otherwise it will overwrite the keyword back upon exit.

IBIS-AMI
TD analysis results are not even similar to Stat results.
DFE TAPS are incorrectly decoded.
Clock Sampling position is not centered in the middle of the eye in TD analysis. BER values are wrong also due to this issue.

AR# 34420
日期 10/23/2012
状态 Active
Type 综合文章
器件 More Less
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