AR# 34539

描述

The following error occurs when I synthesize the VHDL outputs from the Virtex-6 FPGA GTX Transceiver Wizard:

"Error: ../../example_design/rx_sync.vhd(231): Integer literal 1 is not of type ieee.std_logic_1164.std_logic"

This Answer Record discusses the changes that need to be made to the code to work around this problem.

解决方案

The VHDL code mistakenly uses Verilog constant definitions. Changing the following assignments in the rx_sync.vhd module bypasses this error:

RXDLYALIGNRESET <= 1'b0; and RXDLYALIGNDISABLE <= 1'b0;

to:

RXDLYALIGNRESET <= '0'; and RXDLYALIGNDISABLE <= '0';