AR# 34556

描述

The MIG Virtex-6 DDR2/DDR3 designs are characterized with specific termination schemes and I/O Standards. The DDR2 and DDR3 SDRAM Memory Interface Solution > Core Architecture > Design Guidelines section within the Virtex-6 FPGA Memory Interface User Guide (UG406) includes information on termination guidelines and the MIG design's use of I/O Standards.

NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

Termination

Running SI Simulation using IBIS Models is highly recommended for all memory designs. The user guide section noted above includes information on the following:

• Termination guidelines for uni- and bi-directional signals
• Where termination resistors should be placed
• How to properly terminate ODT, CKE, and RESET to adhere to the DDR2 and DDR3 Memory standards initialization processes
  • (Xilinx Answer 36104)- MIG Virtex-6 DDR2/DDR3 - How to properly terminate ODT, CKE, and RESET
• Usage of ODT (at the memory) and DCI (at the memory)
  • The usage of ODT has many advantages including lower power and better signal for the reads along with fewer components on the board and less chance for manufacturing issues.
• (Xilinx Answer 42783)MIG Virtex-6 DDR2/DDR3 - Termination for DM when ODT is used, but not DM

Please read the entire section noted above for full details.

I/O Standards

The MIG tool creates the UCF using the appropriate standard based on input from the GUI. You can find the MIGUCF in either the "example_design/par" or "user_design/par" directories. Only the I/O standards provided in the MIG UCFs have been tested in hardware during MIG characterization.

Revision History

6/22/2011 - Added Answer Record 42783
2/17/2011 - Added Answer Record 36104

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