2. 技术支持
  3. AR# 3542: Bus References in a netlist are different between Synplicity or Cadence or Mentor (xnf) and Foundation and Viewlogic (edif).
  4. AR# 35420: 12.x/11.x ChipScope IBERT - Using LVDS_25 clock for system clock does not enable DIFF_TERM on input

AR# 35420

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12.x/11.x ChipScope IBERT - Using LVDS_25 clock for system clock does not enable DIFF_TERM on input

描述

When I select LVDS_25 as my System Clock input standard, the following error occurs in the Analyzer after attempting to connect to my IBERT core:

"ERROR:XSDB Master could not reset the System Clock. The System Clock is not locked. The System Clock is not running."

How do I work around this error?

解决方案

NOTE: The root cause might be related to (Xilinx Answer 34669). Please review this Answer Record before attempting the work-arounds below.

If you do not have on-board termination and require the use of the DIFF_TERM attribute for your clock, then you can see this problem. Without DIFF_TERM your clock can be incorrectly terminated and, therefore, will not be input to the device correctly; this will affect core operation resulting in the error message specified.

To work around this issue:

CORE Generator

Uncheck the "Implement Design" checkbox in the last CORE Generator customization screen. You can then modify the UCF file produced to add DIFF_TERM to the System Clock.

Example:
#-------------------------------------------------------------------------------------
# System Clock Timing Constraints and PIN LOCs (if applicable)
#-------------------------------------------------------------------------------------
NET "IBERT_SYSCLOCK_P_IPAD" LOC = AE30;
INST "U0/I_USE_SYSCLOCK.I_USE_SYSCLOCK_DIF_INPUT.U_SYSCLOCK_IBUFDS" IOSTANDARD = LVDS_25 | DIFF_TERM="TRUE";;
NET "IBERT_SYSCLOCK_P_IPAD" CLOCK_DEDICATED_ROUTE = FALSE;
NET "U0/ibert_sysclock" PERIOD = 312.5 MHz;
PIN "U0/U_IBERT_CORE/U_MA_DCLK_DIVIDER/mmcm_adv_inst.CLKIN1" CLOCK_DEDICATED_ROUTE = FALSE;

IBERT CORE Generator

After generating the core, open the NCD file in FPGA Editor (DIFF_TERM can be enabled here). Run BitGen again to regenerate the bit file, and then you will have a working core.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
35269 12.x ChipScope Pro - Known Issues for the ChipScope Pro 12.x software N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
34669 ChipScope, Analyzer IBERT - "ERROR:XSDB Master could not reset the System Clock. The System Clock is not locked. The System Clock is not running" N/A N/A
AR# 35420
日期 12/15/2012
状态 Active
Type 综合文章
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