AR# 35954
|Virtex-5 - USERCLKO and CCLK not synchonised in STARTUP_VIRTEX5 when accessing SPI Flash
描述
In XAPP1020, we access configuration SPI Flash by usingSTARTUP_VIRTEX5. But, the input ofSTARTUP_VIRTEX5 USERCLKO is not synchronous with output CCLK from the beginning.解决方案
This is the connection in XAPP1020.
And we assume that the outputSCK (Which is CCLK) will follow the inputUSRCCLKO.However, after configuration theCCLK will keep high no matter what the initial state ofUSRCCLKO. These two signals willbe synchronousonly after the first falling edge ofUSRCCLKO.
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| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 52626 | 7 Series, STARTUPE2 - USRCCLK0 requires three clock cycles to switch CCLK output to User Function | N/A | N/A |