To work around this issue, several lines in the testbench file (sim_tb_top.v) must be modified.
Specifically, inside the memory model instantiations, the variable "i" needs to be changed to "c0_i" (controller 0) and "c1_i" (controller 1) for the ck, ck_n, cke and cs_n connections.
For example, change the following:
.ck (c1_ddr3_ck_p_sdram[(i*C1_MEMORY_WIDTH)/72]),to:
.ck (c1_ddr3_ck_p_sdram[(c1_i*C1_MEMORY_WIDTH)/72]),Once you have changed allfour lines for each controller and re-simulated, the simulation completes successfully.