Port | Dir | Clock Domain | Description |
RXSLIDE | Input | RXUSRCLK2 | RXSLIDE implements a comma alignment bump control. When RXSLIDE is asserted, the byte alignment is adjusted by one bit, which permits determination and control of byte alignment by the FPGA logic. Each assertion of RXSLIDE causes just one adjustment. RXSLIDE must be deasserted for more than four RXUSRCLK2 cycles before it can be reasserted to cause another adjustment. When asserted, RXSLIDE takes precedence over normal comma alignment. For proper operation, user should set the followings: RXENPCOMMALIGN = 0; RXENMCOMMALIGN = 0; RXCOMMADETUSE = 1; |
Attribute | Type | Description |
RX_SLIDE_MODE | String | Defines the RXSLIDE mode. OFF: Default setting. RXSLIDE feature is not used. PCS: PCS is used to perform the bit slipping function. RXSLIDE is driven High for one RXUSRCLK2 cycle to shift the parallel data (RXDATA) to the left by one bit. In this mode, even if the RXRECCLK is sourcing from the RX PMA, the clock phase remains the same. PMA: PMA is used to perform the bit slipping function. RXSLIDE is driven High for one RXUSRCLK2 cycle to shift the parallel data (RXDATA) to the right by one bit. If RXRECCLK is sourcing from the RX PMA, its phase may be changed. This mode provides minimum variation of latency comparing to PCS mode. AUTO: It is an automated PMA mode without using the fabric logic to monitor the RXDATA and issue RXSLIDE pulses. In this mode, RXSLIDE is ignored. In PCIe applications, it is set to AUTO for FTS lane deskew. |
RX_SLIDE_AUTO_WAIT | Integer | Defines how long the PCS (in terms of RXUSRCLK clock cycle) waits for the PMA to auto slide before checking the alignment again. Valid setting is from 0 to 15. Default value is 5. Use only recommended values from the Virtex-6 FPGA GTX Transceiver Wizard. |