AR# 38506

描述

The quality of the reference clock supplied to the RXPLL or TXPLL in the Virtex-6 GTX Transceiver can greatly impact the performance of the transmit jitter and receive jitter tolerance. Jitter or phase noise from the reference clockplays an important roll indetermining this performance; phase noise being the preferred specification method as it allows the designer to incorporate thevarious frequency components that a time based jitter specification might overlook.

This Answer Record contains the reference clock phase noise limits that Xilinx recommends based on the PLL settings being used.

解决方案