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  3. AR# 39022: MIG Virtex-6 DDR2/DDR3 - How does adjusting the polarity of DYNCLKDIVSEL during the CLKDIV Calibration Stage increase timing margin?

AR# 39022

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MIG Virtex-6 DDR2/DDR3 - How does adjusting the polarity of DYNCLKDIVSEL during the CLKDIV Calibration Stage increase timing margin?

描述

How does adjusting the polarity of DYNCLKDIVSEL during the CLKDIV Calibration Stage improve timing margin? If CPT clock lands near half-rate CPT clock it seems that inverting CLKDIV would make no difference.

Note:Xilinx recommends existing Virtex-6 DDR2/DDR3 designs upgrade to MIG 3.6 to include this calibration stage.Details on this recommendation are noted below.

Note:This Answer Record is a part of the Xilinx MIG Solution Center(Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

There are essentiallythree clock domain transfer points in the ISERDES as DQ data is captured and eventually appears at the Q outputs of the ISERDES:
  • Stage 1: Data captured using CPT clock (full-rate capture)
  • Stage 2: Data transferred to half-rate CPT clock domain
    • This uses a divide-by-2 version of the CPT clock. Each ISERDES generates its own version of this half-rate clock.
  • Stage 3: Data transferred from divide-by-2 CPT clock to CLKDIV
The transfer of interest here is Stage 3, where data is transferred between divide-by-2-CPT and CLKDIV. In this case, selectively inverting CLKDIV within the ISERDES can help within timing. If you transfer data directly between the CPT clock and the CLKDIV, then whether you invert the CLKDIV signal or not has no affect on the timing.

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
37968 MIG Virtex-6 DDR2/DDR3 - Additional Calibration Stage (CLKDIV Calibration Stage) Added To Calibrate the Timing of the BUFIO to BUFR Transfer N/A N/A
AR# 39022
日期 12/15/2012
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Type 综合文章
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