AR# 39430

描述

Bits 4 and 5 of the POWER_SAVE attribute on the Virtex-6 GTX Transceiver must be set to 2'b11 to bypass the delay aligner per the GTX Delay Aligner Errata item discussed in the following errata (EN142):

https://www.xilinx.com/support/documentation/errata/en142.pdf

The delay aligners lie in the TXOUTCLK and RXRECCLK clock paths and add or remove delay from that path to ensure that RX/TXUSRCLK and the internal parallel clock stay in phase over temperature and voltage variation following the phase alignment procedure that is required when the TX buffer or RX elastic buffer is bypassed.

When the transmitter delay aligner is used, TXOUTCLK can occasionally output a short clock pulse that could cause transmit data errors. When the receiver delay aligner is used, the RXRECCLK can occasionally output a short clock pulse that could cause receiver data errors. If these clocks are used by other logic in the FPGA, incorrect user logic behavior can result. POWER_SAVE[4] = 1'b1 selects a clock path which bypasses the transmit delay aligner and POWER_SAVE[5] = 1'b1 selects a path which bypasses the receive delay aligner.

This Answer Record contains information on specific work-arounds for the GTX Delay Aligner Errata item discussed in EN142. The discussion below is broken into three sections:

1. Protocol specific solutions for Xilinx IP
2. Generic solutions for applications which require TX or RX buffer bypass, broken down by application line rate and device
3. Additional Notes

解决方案

Protocol Specific Solutions

These solutions pertain only to the Xilinx IP which utilize either the TX or RX buffer bypass feature and are broken out by protocol. Each protocol needs to follow the generic recommendations listed further below, including the maximum temperature/voltage variations from the time phase alignment is completed. Each solution below still needs to follow the appropriate temperature/voltage limits following the phase alignment procedures that are mentioned in the Generic Solutions.

PCI Express

Both Gen 1 and Gen 2 PCI Express bypass the TX buffer to minimize TX lane to lane skew. For more information, see (Xilinx Answer 39456).

XAUI bypasses the TX buffer to minimize TX lane-to-lane skew. For smaller devices (as listed above), a BUFG can be used and the only modification needed is setting POWER_SAVE[5:4] on the GTX to 2b11 per the errata.

For larger devices, an MMCM is also needed, as XAUI uses a 20-bit internal interface. For more details on how to make these changes to the core, see (Xilinx Answer 39492)

RXAUI bypasses the TX buffer to minimize TX lane-to-lane skew. The integrated wrapper uses an MMCM to generate TXUSRCLK and TXUSRCLK2, and TXOUTCLK already drives the MMCM directly with no BUFG in the path.

There are several changes needed to the wrapper: insert a BUFG in the MMCM feedback path, modify the POWER_SAVE[5:4] on the GTX to 2b11 per the errata, and lock the MMCM to the correct clocking region as determined via the Virtex-6 FPGA Package and Pinout Guidelines (UG365). For more information on how to make these changes, see (Xilinx Answer 39493). CPRI and OBSAI bypass both the TX and RX buffers to ensure deterministic latency through the data path.

For CPRI work-arounds, see (Xilinx Answer 39992) For OBSAI work-arounds, see (Xilinx Answer 39993).

The TX Clocking Structure requires no modification of rates at or below 3.072 Gb/s. Above 3.072 Gb/s, an MMCM must be used to generate TXUSRCLK and TXUSRCLK2. The MMCM must be driven directly by TXOUTCLK with no intermediate BUFG, and the MMCM must be constrained to the same clocking region as the GTX providing TXOUTCLK. Clocking regions and appropriate locations can be determined via theVirtex-6 FPGA Package and Pinout Guide (UG365): http://www.xilinx.com/support/documentation/user_guides/ug365.pdf

The RX clocking structure needs to use BUFRs to provide RXUSRCLK and RXUSRCLK2 in all cases. The BUFR needs to be driven directly from RXRECCLK in the same fashion as the BUFR use case mentioned below.

Generic Solution

To ensure enough system margin, only particular clocking schemes can be supported when bypassing either the TX or RX buffers. These vary based on the line rate at which the GTX is running, the internal data width and the device used, and are different between the TX and RX interfaces.

Please note that these requirements are only necessary for those applications, either custom or utilizing templates or IP, that bypass the TX or RX buffers by setting TX_BUFFER_USE= FALSE or RX_BUFFER_USE= FALSE.

The supported clocking topologies based on device, internal data width, and line rate are defined first and are followed by in-depth descriptions of how those clocking topologies need to be implemented.

TX Solutions

These solutions apply to the transmit domain when the TX Buffer is bypassed.

The use models listed in each table correspond to the in-depth descriptions of the same name in the next section of this Answer Record.

LX75T, LX130T, LX195T, LX240T, HX250T, HX255T, HX380T:

* Full temperature range, depending on the temperature grade of the device, is supported with +/-50mV of Vccint variance following the phase alignment procedure. +/-100mV of Vccint variance following the phase alignment procedure is supported in conjunction with a maximum +/-20C temperature change. Temperatures are measured at the junction.


LX365T, LX550T, SX315T, SX475T, HX565T:

* Full temperature range, depending on the temperature grade of the device, is supported with +/-50mV of Vccint variance following the phase alignment procedure. +/-100mV of Vccint variance following the phase alignment procedure is supported in conjunction with a maximum +/-40C temperature change. Temperatures are measured at the junction.

RX Solutions

LX75T, LX130T, LX195T, LX240T, HX250T, HX255T, HX380T:

(1) Full temperature range, depending on the temperature grade of the device, is supported with +/- 50 mV of Vccint variance following the phase alignment procedure.

(2) +/-100mV of Vccint variance following the phase alignment procedure is supported in conjunction with a maximum +/-20C temperature change.

Temperatures are measured at the junction.

LX365T, LX550T, SX315T, SX475T, HX565T:

(1) Full temperature range, depending on the temperature grade of the device, is supported with +/-50mV of Vccint variance following the phase alignment procedure. +/-100mV of Vccint variance following the phase alignment procedure is supported in conjunction with a maximum +/-50C temperature change.

(2) Full temperature range, depending on the temperature grade of the device, is supported with +/-50mV of Vccint variance following the phase alignment procedure.

Temperatures are measured at the junction.

BUFG

Any clocking scheme outlined in theVirtex-6 GTX Transceivers Users Guide can be supported.

BUFR

One of the BUFRs in a clocking region must be used to generate USRCLK and USRCLK2, and must be driven by the appropriate GTX output clock, TXOUTCLK for TX Buffer Bypass or RXRECCLK for RX Buffer Bypass.

Some of the Virtex-6 devices have two BUFRs per clocking region while the larger devices (LX365T, LX550T) have four BUFRs per clocking region. Each GTX Quad spans an entire clocking region, so only two or four BUFRs can be used per Quad depending on the device.

MMCM
For situations where an MMCM must be used, USRCLK and USRCLK2 must be driven directly without an intermediate BUFG by the appropriate GTX output clock, TXOUTCLK for TX Buffer Bypass or RXRECCLK for RX Buffer Bypass. 

In cases where multiple TX lanes are using the same reference clock and USRCLK/USRCLK2 rates, one MMCM can be used. As each GTX Quad spans an entire clocking region and there are two available MMCMs per clocking region, the MMCM used must be constrained to a location within that region, otherwise a BUFG is automatically inserted.

There are two ways to ensure this occurs. The first is to use the "buffer_type" XST attribute on the clock net and set it to "none." The second is to use a UCF LOC constraint to force the MMCM to a pre-selected location. 

These locations can be determined via theVirtex-6 Package and Pinout Guide(UG365): http://www.xilinx.com/support/documentation/user_guides/ug365.pdf

The CLKFBIN needs to be provided as illustrated below, though USRCLK/USRCLK2 can be provided via any of the CLKx outputs through a BUFG. 

Internal feedback should not be used and the feedback path requires a BUFG. Utilizing CLKFBOUT to provide USRCLK is a viable way to save a BUFG, as CLKIN is provided by a clock guaranteed to be the same rate as the USRCLK.

Additional Notes:
1. Modifying the POWER_SAVE attribute will result in software errors in 12.2 12.3 and 12.4. (Xilinx Answer 39434) contains a method for working around these errors.
2. TX/RXDLYALIGNDISABLE can be tied to 1'b1, but it is not required to disable the delay aligner.
3. These recommendations will be rolled into the Virtex-6 FPGA GTX User's Guide (UG366) in the future.

链接问答记录

相关答复记录