This section of the MIG Design Assistant focuses on Board Layout Guidelines for the Spartan-6 MCB designs. Please select from the below options to find information related to your specific question.
NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
The Spartan-6 MCB design requires thatspecific board layout rules be followed in order for the design to behave correctly in hardware. The following Answer Records provide detailed information on the board layout requirements. Information can also be found in the"Designing with the MCB">"PCB Layout Considerations" section ofthe Spartan-6 FPGA Memory Controller User Guide(UG388):
http://www.xilinx.com/support/documentation/ip_documentation/ug388.pdf
On top of following these rules, it is strongly recommended users run SI Simulations using IBIS Models to verify signal integrity:
If after verifying these rules have been followed and errors are still seen in hardware, please refer back to the main Hardware section of this Design Assistant to look into Pin-out Requirements and Hardware Debug.
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
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43541 | MIG Spartan-6 MCB - Traffic Generator Details and Usage | N/A | N/A |
43537 | MIG Spartan-6 MCB - Debugging Calibration Failures | N/A | N/A |
40868 | MIG Spartan-6 MCB - Simultaneously Switching Noise (SSN) Calculation | N/A | N/A |
40867 | MIG Spartan-6 MCB - Signal Integrity Simulation Using IBIS | N/A | N/A |
37502 | MIG Design Assistant - Spartan-6 FPGA Hardware | N/A | N/A |
34708 | MIG Virtex-6 DDR2/DDR3 - SI Simulation using IBIS | N/A | N/A |
40771 | MIG Spartan-6 MCB - Trace Matching Guidelines | N/A | N/A |
40778 | MIG Spartan-6 MCB - Termination and I/O Standard Guidelines | N/A | N/A |
AR# 40775 | |
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日期 | 02/27/2013 |
状态 | Active |
Type | 综合文章 |
器件 | |
IP |