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  3. AR# 41706: MIG 7 Series - Can FPGA banks be shared among memory interfaces?

AR# 41706

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MIG 7 Series - Can FPGA banks be shared among memory interfaces?

描述

Is it possible to share an FPGA bank between two MIG interfaces?

If a bank containing one memory interface contains unused T* byte groups, can these unused byte groups be assigned to a different memory controller?

解决方案

No, FPGA banks cannot be shared between multiple memory controllers. 

Each MIG interface requires a unique PHY Control Block in all interface banks.

The PHY Control Block is dedicated logic that controls the FIFOs and Phasers within the bank.

Both Address/Control and Data Byte Groups use the PHY Control Block within the bank and only one PHY Control Block exists in an FPGA bank.

Therefore, it is not possible to share a bank between two interfaces.

This is documented in the Design Guidelines section of the 7 Series FPGAs Memory Interface Solutions User Guide (UG586)


链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
51317 MIG 7 Series DDR2/DDR3 - Verify pin-out/banking requirements are met N/A N/A
51676 MIG 7 Series Solution DDR2/DDR3 - Supported Features N/A N/A

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
60952 MIG 7 Series - Pinout validation in Fixed Pinout Mode does not check against multiple controllers N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
60952 MIG 7 Series - Pinout validation in Fixed Pinout Mode does not check against multiple controllers N/A N/A
AR# 41706
日期 08/13/2014
状态 Active
Type 综合文章
器件
IP
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