2. 技术支持
  3. AR# 4275: M1.5: WARNING:basts:158 - PERIOD TIMESPEC 'xxx' has TIMEGRP 'xxx' which contains only PAD elements. Or mixture of PADs and synchronous elements.
  4. AR# 42757: Virtex-7, Kintex-7, 13.2, 13.3 - GTX IBERT-"ERROR:Bitgen:342" Occurs During Bitstream Generation of GTX IBERT core

AR# 42757

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Virtex-7, Kintex-7, 13.2, 13.3 - GTX IBERT-"ERROR:Bitgen:342" Occurs During Bitstream Generation of GTX IBERT core

描述

When generating a bitstream for the Kintex-7 GTXIBERT core or virtex-7 GTX IBERT Core in 13.2 or 13.3, the following error occurs:

"ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD). This maycause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To prevent this error, it is highly suggested to specify all pin locations and I/O standards to avoid potential contention or conflicts and allow proper bitstreamcreation. To demote this error to a warning and allow bitstream creationwith unspecified I/O location or standards, you may apply the following bitgen switch: -g UnconstrainedPins:Allow. This message applies to the following I/O ports:IBERT_SYSCLOCK_N_IPAD."

This answer record details the solution to work around the error.

解决方案

This error message occurs because BitGen now performs a DRC check to ensure that all differential I/O pins have both the P and N side pins constrained. The Integrated Bit Error Ratio Tester(IBERT) currently only constrains the P side of the differential pair. To work around this issue, follow the solution below:

1. When generating the IBERT core in Core Generator, uncheck the Generate Bitstream option and generate the core.
2.Create the design.
3. Go to the "example_design" directory and open the "chipscope_ibert_top.ucf" file.
4. Find the "System Clock Timing Constraints" section and add a line to constrain the N side of the differential system clock pair. The UCF should now look something like:

INST "U_SYSCLOCK_IBUFDS" IOSTANDARD = LVDS_25;
NET "IBERT_SYSCLOCK_P_IPAD" LOC = AD12;
NET "IBERT_SYSCLOCK_ N_IPAD" LOC = AD11;

5. Make sure that you are locating the N side of the system clock to the appropriate pin for your differential pair.
6. Savethe ucf file and navigate to the "implement" directory. You can now run the implement.sh (for linux) or implement.bat (for windows) to run through an implementation and generate a bit file.

Alternate Solution

If, for some reason, you do not want to use theLOC constraint on the N side of the system clock, you can alternatively use the solution below to work around this issue. It is highly recommended that you follow the solution above and use the LOC constraint on the N side of the clock manually.

1. Create the design.
2. Go to the "implement" directory and modify the "implement.sh" (for linux) or "implement.bat" (for windows) script to include the following option: -g UnconstrainedPins:Allow. TheBitGen command in the script file should look something like:

bitgen -d -g UnconstrainedPins:Allow -g GWE_cycle:Done -g GTS_cycle:Done
-g DriveDone:Yes -g StartupClk:Cclk -w example_chipscope_ibert_top.ncd

3. Run the implementation script.

This is a known issue that will be fixed in 13.4.

Please note that this BitGen issue can affect other parts of your design as well if you are only constraining the P side of a differential I/O pair. For more information on this BitGen issue, please see (Xilinx Answer 42678).

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
42678 13.2 Bitgen - Incorrect occurrence of "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)" N/A N/A
AR# 42757
日期 05/19/2012
状态 Active
Type 已知问题
器件
Tools
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