AR# 42806

描述

解决方案

Introduction

For installation instructions for this release, go to: http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

For system requirements, see: http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm

This file contains release notes for the Xilinx LogiCORE IP Virtex-6 FPGA GTX Transceiver Wizard v1.10 solution. For the latest core updates, see the product page at: http://www.xilinx.com/content/xilinx/en/products/intellectual-property/v6_fpga_gtx_transceiver_wizard.html

New Features

• ISE 13.2 software support
• Auto Upgrade Support has been added. Older versions of the core- 1.4, 1.5, 16, 1.7, 1.8,1.9 can be upgraded to 1.10
• Added support for 3G-SDI protocol template

Supported Devices

The following device families are supported by the core for this release:

• Virtex-6 XC CXT/LXT/SXT/HXT
• Virtex-6 XQ LXT/SXT   
• Virtex-6 -1L XC LXT/SXT

Resolved Issues

• CR 608107 - Until v1.9 version of the core, 8b/10b can only be selected as encoding when a data path width of 10, 20 or 40 is selected. This has been modified to 8, 16 or 32.
• CR 596296 - Added support to bring GTXTEST[1] to wrapper input when requested.
• CR 596294 - Updated logic not to provide RX_RESET after double_reset_pulse if RX Clock Source is from RXRECCLK.
• CR 591651 - Updated TCL such that summary page shows correct line rate.

Known Issues

The following are known issues for v1.10 of this core at time of release:

• Delay Aligner in both TX and RX is bypassed. For the clocking use models, and detailed information please refer to AR 39430.
• Support for Virtex-6Q Lower Power devices are not present in Virtex-6 GTX Wizard. When a user attempts to generate a core with any of the qvirtex6l device packages and run implementation, it fails in MAP stage as the refclk pin locations in UCF are not correctly generated by the core. Please refer to answer records for detailed work-around.

The most recent information, including known issues, work-arounds, and resolutions for this version is provided in the IP Release Notes Guide located at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf

Technical Support

To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.

Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.

Other Information

• Fiber Channel 1G, 2G, 4G, OC48, SATA-I and SATA-II protocol files are not tested for compliance.
• For SATA-II protocol, set TX/RXPLL_DIVSEL_FB=2, TX/RXPLL_DIVSEL_REF=2, TX/RXPLL_DIVSEL_OUT=1.
• The transceiver attributes of v1.10 version of this core support 2.01 silicon revision.

Core Release History

 Date        By            Version      Description
 ================================================================================
 06/22/2011  Xilinx, Inc   1.10         ISE 13.2 support
 03/01/2011  Xilinx, Inc   1.9          ISE 13.1 support
 12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
 09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
 07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
 04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
 12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
 09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
 06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
 04/24/2009  Xilinx, Inc.  1.1          ISE 11.1 support
 ================================================================================

链接问答记录

相关答复记录