2. 技术支持
  3. AR# 4283: F1.4 Simulator: Simulating FPGA Express Netlist returns Warning 9218: unknown pin name
  4. AR# 42832: MIG 7 Series v1.2-v1.4 DDR3 - FULL calibration mode violates tREFI requirement

AR# 42832

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MIG 7 Series v1.2-v1.4 DDR3 - FULL calibration mode violates tREFI requirement

描述

MIG 7 Series v1.2-v1.4 DDR3 designs exceed the maximum refresh time in FULL calibration mode (SIM_BYPASS_INIT_CAL="SIM_INIT_CAL_FULL").

解决方案

The JEDEC specifications state that a maximum of eight refreshes can be postponed up to 9*tREFI periods, and after that refreshes should be pulled in to meet the tREFI time.

The MIG 7 Series v1.2-v1.4 DDR3 design is violating this specification when SIM_BYPASS_INIT_CAL="SIM_INIT_CAL_FULL".

There is currently no workaround, so these violations can be ignored for now.

This issue is due to be fixed in MIG v1.5 to be released in ISE 14.1.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
41227 MIG 7 Series v1.2 - Release Notes and Known Issues for ISE Design Suite 13.2 N/A N/A
43099 MIG 7 Series v1.3 - Release Notes and Known Issues for ISE Design Suite 13.3 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
43099 MIG 7 Series v1.3 - Release Notes and Known Issues for ISE Design Suite 13.3 N/A N/A
41227 MIG 7 Series v1.2 - Release Notes and Known Issues for ISE Design Suite 13.2 N/A N/A
45195 MIG 7 Series - Release Notes and Known Issues for All ISE versions and Vivado 2012.4 and older tool versions N/A N/A
AR# 42832
日期 08/13/2014
状态 Active
Type 已知问题
器件 More Less
IP
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