AR# 44010

描述

解决方案

This article describes how to configure the Kintex-7 transceivers with the correct BIAS_CFG setting. Please ensure the corrections as outlined in (Xilinx Answer 42626) are carried out.

You must instantiate the GTXE2_COMMON block in every quad used in the design. Add the following code to the <component_name>/example_design/gtx_and_clocks/gtx/v7_gtwizard.vhd file:

signal qpll_clk : std_logic;

gtxe2_common_0_i : GTXE2_COMMON

generic map

(

Simulation Attributes

SIM_RESET_SPEEDUP => ("TRUE"),
SIM_QPLLREFCLK_SEL => ("001"),
SIM_VERSION => ("1.0"),

------------------COMMON BLOCK---------------

BIAS_CFG => (x"0000042000001000"),
COMMON_CFG => (x"00000000"),
QPLL_CFG => (x"06801C1"),
QPLL_CLKOUT_CFG => ("0000"),
QPLL_COARSE_FREQ_OVRD => ("010000"),
QPLL_COARSE_FREQ_OVRD_EN => ('0'),
QPLL_CP => ("0000011111"),
QPLL_CP_MONITOR_EN => ('0'),
QPLL_DMONITOR_SEL => ('0'),
QPLL_FBDIV => ("0011100000"),
QPLL_FBDIV_MONITOR_EN => ('0'),
QPLL_FBDIV_RATIO => ('1'),
QPLL_INIT_CFG => (x"000028"),
QPLL_LOCK_CFG => (x"01D0"),
QPLL_LPF => ("1111"),
QPLL_REFCLK_DIV => (1)

)
port map
(

------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------

DRPADDR => x"00",
DRPCLK => '0',
DRPDI => x"0000",
DRPDO => open,
DRPEN => '0',
DRPRDY => open,
DRPWE => '0',

---------------------- Common Block - Ref Clock Ports ---------------------

GTREFCLK0 => GT0_GTREFCLK0_IN,
GTGREFCLK => '0',
GTNORTHREFCLK0 => '0',
GTNORTHREFCLK1 => '0',
GTREFCLK1 => '0',
GTSOUTHREFCLK0 => '0',
GTSOUTHREFCLK1 => '0',

------------------------- Common Block - QPLL Ports ------------------------

QPLLFBCLKLOST => open,
QPLLLOCK => open,
QPLLLOCKDETCLK => GT0_GTREFCLK0_IN,
QPLLLOCKEN => '1',
QPLLOUTCLK => qpll_clk,
QPLLOUTREFCLK => open,
QPLLOUTRESET => '0',
QPLLPD => '0',
QPLLREFCLKLOST => open,
QPLLREFCLKSEL => "001",
QPLLRESET => GT0_GTTXRESET_IN,
QPLLRSVD1 => "0000000000000000",
QPLLRSVD2 => "11111",
RCALENB => '0',
REFCLKOUTMONITOR => open,

----------------------------- Common Block Ports ---------------------------

BGBYPASSB => '0',
BGMONITORENB => '0',
BGPDB => '1',
BGRCALOVRD => "00000",
PMARSVD => "00000000",
QPLLDMONITOR => open

);

To prevent the tools from optimizing the common block away the QPLLOUTCLK output (qpll_clk in the code above) should be routed through the transceiver wrapper to the QPLLCLK input of the GTXE2_CHANNEL instance.

For more information, see the LogiCORE CPRI Release Notes and Known Issues, see (Xilinx Answer 36969).

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