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  3. AR# 47921: Zynq-7000 SoC - Processing System IP and Related Industry Standards

AR# 47921

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Zynq-7000 SoC - Processing System IP and Related Industry Standards

描述

The Zynq-7000 SoC devices include IP cores that were acquired from 3rd party suppliers.

解决方案

Visit the documentation section of the Zynq-7000 SoC Solution Center for more information: Zynq Solution Center - Documentation.

Zynq-7000 Third Party IP List

PS Module
IP Vendor
Documentation
APU CPU
ARM Cortex-A9 MPCore

ARM Documents (version r3p0):
 * Architecture Reference Manual (Need to register with ARM)
 * Cortex-A Series Programmer's Guide.
 * Cortex-A9 Technical Reference Manual (TRM).
 * Cortex-A9 MPCore TRM (DDI0407F) ACP, timer/watchdogs, events, interrupts and SCU.
 * Cortex-A9 NEON Media Processing Engine TRM.
 * Cortex-A9 Floating-Point Unit TRM.

APU L2 Cache
ARM, PL310
ARM Document: (version r3p2-50rel0)
 * AMBA Level 2 Cache Controller (L2C-310) TRM
CPU DebugARM, CoreSightARM Documents:
 * CoreSight v1.0 Architecture Spec  ATB Bus, and Authentication
 * CoreSight Program Flow Trace Architecture Specification
 * Debug Interface v5.1 Architecture Specification
 * Debug Interface v5.1 Architecture Specification Supplement
 * CoreSight Components TRM  ECT, ETB, ITM, DAP and TPIU.
 * CoreSight PTM-A9 TRM
 * CoreSight Trace Memory Controller Technical Reference Manual
GICARM Generic Interrupt ControllerARM Documents:
* Generic Interrupt Controller v1.0 Architecture Specification (IHI 0048B)
* ARM Generic Interrupt Controller PL390 TRM (DDI0416B)
SMC
ARM Static Memory Controller, PL353  
ARM Document (revision r2p1):
 * PrimeCell Static Memory Controller (PL350 series) Technical Reference Manual, 12 October 2007 (ARM DDI 0380G)
DMAC
ARM DMA Controller, PL330

ARM Document (version r1p1):
 * PrimeCell DMA Controller (PL330) Technical Reference Manual
 * Application Note 239: Example programs for CoreLink DMA Controller DMA-330

PS Interconnect
ARM, NIC-301 rev r2p2
ARM Document:
 * AMBA Specification Revision 2.0, 1999 (IHI 0011A)
DDRC
Synopsys, IntelliDDR rev A07
USB
Synopsys, Atlantic revision 2.20a
USB Standards:
 * USB 2.0 Specification
 * UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1
 * Intel Corp., EHCI Specification for USB, v1.0, 2002
 * ISO 11898 Standard USB Association,
SWDT timer
Cadence, rev07
 * Cadence, Watchdog Timer (SWDT) Specification
I2C
Cadence, rev r1p10
GigE
Cadence, rev r1p23

Ethernet Standard:
 * IEEE 802.3-2008 - IEEE Standard for Information technology-Specific requirements - Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, 2008

SPI
Cadence, ref r1p06
See Zynq-7000 TRM.
UART
Cadence, ref r1p08
See Zynq-7000 TRM.
TTC timer
Cadence, ref 06
See Zynq-7000 TRM.
SD controller
Arasan, rev 8.9A_apr02nd_2010
 * SD Association, Part A2 SD Host Controller Spec Ver2.00 Final 070130
 * SD Association, Part E1 SDIO Specification Ver2.00 Final 070130
 * SD Group, Part 1 Physical Layer Specification Ver2.00 Final 060509
CAN controllerXilinx * BOSCH, CAN Specification Version 2.0 PART A and PART B, 1991
 

 

Revision History

August 2013: revamped.

AR# 47921
日期 05/25/2018
状态 Active
Type 解决方案中心
器件
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