AR# 50795

描述

Timing failures might occur in the XAUI core Example Design if targeting 7 series FPGAs.

解决方案

To work around this issue, the core can be constrained to be placed close to the selected GTs.

In the XDC file, one of the following area groups can be used:

A.  Create a slice range area group:

create_pblock pblock_xaui_block
add_cells_to_pblock [get_pblocks pblock_xaui_block]  [get_cells -quiet [list xaui_block]]
resize_pblock [get_pblocks pblock_xaui_block] -add {SLICE_XnnnYnnn:SLICE_XnnnYnnn}

B. If a clock region is desired instead of a slice range, the following could be used:

create_pblock pblock_xaui_block
add_cells_to_pblock [get_pblocks pblock_xaui_block]  [get_cells -quiet [list xaui_block]] 
resize_pblock [get_pblocks pblock_xaui_block] -add {CLOCKREGION_X1Y2}