I am attempting to exercise the interfaces on the Virtex-7 FPGA VC709 Connectivity Kit.
What tests can be run to ensure that the interfaces are working correctly?
Virtex-7 FPGA VC709 Connectivity Kit Documentation and Example Designs referenced below can be found on the VC709 Support page.
| Feature | Test Design | Notes |
|---|---|---|
| -- Configuration Interfaces -- | ||
| Configuration Mode Switches | VC709 User Guide (UG887) | Table 1-2 has the valid settings. Assuming configuration source is correctly programmed, this can test the mode pins |
| Configuration USB JTAG Port | VC709 BIST (XTP232) | See "Program VC709 with BIST Design" section |
| Configuration BPI Flash | VC709 BIST (XTP232) | |
| -- Board Feature Interfaces -- | ||
| Board DDR3 SODIMM (2) | VC709 BIST (XTP232) | Also tested in the VC709 MIG Example Design |
| Board PCIe Edge Connector | VC709 PCIe Example Design (XTP237) | |
| Board SFP Connector | VC709 GTH IBERT Example Design (XTP234) | Requires Molex 74765-0904 |
| Board Oscillator (200 MHz, Differential) | VC709 BIST (XTP232) | The default BIST examples use the socket clock |
| Board USB Serial UART | VC709 BIST (XTP232) | |
| Board Power Monitoring Interface (TI PMBus) | (Xilinx Answer 37561) | Requires the TI USB Interface Adapter EVM; see (Xilinx Answer 54022) |
| Board I2C Interface | VC709 BIST (XTP232) | |
| Board FMC-HPC Connector | XM105 User Guide (UG537) | Page 29. This is the User Guide for the XM105 Mezzanine Debug Card. This card has DS5, DS6, and DS7, which indicate good power to the board. Debug strategies will vary depending on the specific mezzanine card being used |
| -- Transceiver Interfaces -- | ||
| Transceiver RefCLK (Differential) | VC709 GTH IBERT Example Design (XTP234) | This is the IBERT Example Design and could be modified to use SMA RefCLK |
| Transceiver SMA Connectors (Differential) | VC709 GTH IBERT Example Design (XTP234) | |
| -- User Specified Interfaces -- | ||
| User CLK Socket Connector (Single-Ended) | VC709 BIST (XTP232) | All designs in the BIST use the socket clock source |
| User SMA CLK Connectors (Differential) | none available | These are completely user-driven I/O. A good test would be loop back or monitoring differential I/O on a scope |
| User SMA Connectors (Differential) | none available | These are completely user-driven I/O |
| User LEDs | VC709 BIST (XTP232) | |
| User DIP Switches | VC709 BIST (XTP232) | |
| User Pushbuttons | VC709 BIST (XTP232) | |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 43748 | Xilinx Boards and Kits - Debug Assistant | N/A | N/A |
| 54355 | Virtex-7 FPGA VC709 Connectivity Kit - Board Debug Checklist | N/A | N/A |
| AR# 54568 | |
|---|---|
| 日期 | 01/20/2014 |
| 状态 | Active |
| Type | 综合文章 |
| Boards & Kits | |