AR# 55011

描述

Version Found:   v1.8
Version Resolved: For ISE, see (Xilinx Answer 45195).
                                  For Vivado, see (Xilinx Answer 54025)

The MIG 7 Series DDR3 design includes a "Debug Signals" option which generates ChipScope ILA and VIO cores with connections to the appropriate debug signals within the design. The VIO includes a DQS byte select to force the debug outputs shown in the ChipScope tool to be related specifically to the byte on dbg_dqs. For PRBS Read Leveling calibration, dbg_dqs is not connected and therefore, the results shown will be for the last byte group calibrated.

解决方案