AR# 55129

描述

Version Found: v1.5
Version Resolved: See (Xilinx Answer 45195) and (Xilinx Answer 54025)

Cypress memory models fail simulation with watch dog timer errors during calibration for MIG QDRII+ designs with BL=2 and DATA_WIDTH=18.

解决方案

This is a known issue with the Cypress BL2 memory model and can be worked around by making the following changes in the CY7C25442KV18.v model:

always @(posedge IoutClk)
  begin
    if (rpen_o_o == 0)
      chip_oe = `tchz 1;
    else
      chip_oe = `tchz 0;
  end

always @(posedge IoutClk)
  begin
    if (rpen_o == 0)
      chip_oe = `tchz 1;
    else
      chip_oe = `tchz 0;
  end

Revision History
04/03/2013 - Initial release

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