AR# 55245

描述

This answer record shows the support of some of the Vivado synthesis properties in XDC:

SHREG_EXTRACT, ROM_STYLE, RAM_STYLE, MAX_FANOUT

Example codes and constraints are attached at the end of this answer record.

解决方案

Support for these properties:

SHREG_EXTRACT:

This property instructs the synthesis tool to infer shift registers.

Example: set_property SHREG_EXTRACT NO [get_cells shreg_reg*]

This property works in the current version of the tool and can be set via XDC.

ROM_STYLE:

This property instructs the synthesis tool to infer a ROM memory.

Example: set_property ROM_STYLE BLOCK [get_cells do0_1]

This property works in the current version of the tool and can be set via XDC.

RAM_STYLE:

This property instructs the synthesis tool to infer RAM memory.

Example:  set_property RAM_STYLE DISTRIBUTED [get_cells hier mem_reg*]

This property works in the current version of the tool and can be set via XDC.

MAX_FANOUT:

This property instructs the synthesis tool on the fanout limits for registers and signals.

Example:  set_property MAX_FANOUT 10 [get_nets ena]

This property is working in the current version of tool.

For example, "report_property [get_nets count[31\\\]]" will report that the MAX_FANOUT attribute was set to 10 in the synthesized netlist.

Codes and Constraints examples:

Table 1-1

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