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  4. AR# 56387: MIG 7 Series - timing failures within the VIO/ILA 2.0 can occur across all interfaces when using multiple clock domains

AR# 56387

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MIG 7 Series - timing failures within the VIO/ILA 2.0 can occur across all interfaces when using multiple clock domains

描述

Version Found: v2.0
Version Resolved: See (Xilinx Answer 54025)

Timing failures within the VIO/ILA 2.0 can occur when using the MIG 7 series designs when multiple VIO's and ILA's are instantiated with multiple clock domains. This has only been seen when using multi-controller designs, but it could occur with single interface designs as well if they contain multiple VIO's and ILA's using with different clock domains. The default MIG generated example design will not fail as it only uses a single clock domain for the VIO's and ILA's. 

Example timing failure:
Slack (VIOLATED) :        -1.546ns  (required time - arrival time)
 


  Source:                 CHIPSCOPE_INST.u_ila_rldx/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[7]/C


                            (rising edge-triggered cell FDRE clocked by clk_pll_i_1  {rise@0.000ns fall@4.000ns period=8.000ns})


  Destination:            CHIPSCOPE_INST.u_ila_rldx/inst/ila_core_inst/u_ila_regs/reg_81/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[7]/D


                            (rising edge-triggered cell FDRE clocked by clk_pll_i_1  {rise@0.000ns fall@4.000ns period=8.000ns})





Slack (VIOLATED) :        -1.039ns  (required time - arrival time)


  Source:                 u_my_mig/c0_u_qdr_phy_top/u_qdr_phy_write_top/u_qdr_phy_write_init_sm/phy_init_cs_reg[7]/C


                            (rising edge-triggered cell FDRE clocked by clk_pll_i  {rise@0.000ns fall@2.000ns period=4.000ns})


  Destination:            CHIPSCOPE_INST.u_ila_rldx/inst/ila_core_inst/shifted_data_in_reg[6][541]_srl7/D


                            (rising edge-triggered cell SRL16E clocked by clk_pll_i_1  {rise@0.000ns fall@4.000ns period=8.000ns})





Slack (VIOLATED) :        -2.188ns  (required time - arrival time)


  Source:                 u_my_mig/c2_u_rld_memc_ui_top_std/u_rld_phy_top/u_qdr_rld_phy_read_top/u_qdr_rld_phy_read_stage2_cal/cal_done_reg/C


                            (rising edge-triggered cell FDRE clocked by clk_pll_i_2  {rise@0.000ns fall@3.333ns period=6.666ns})


  Destination:            CHIPSCOPE_INST.u_ila_rldx/inst/ila_core_inst/shifted_data_in_reg[6][541]_srl7/D


                            (rising edge-triggered cell SRL16E clocked by clk_pll_i_1  {rise@0.000ns fall@4.000ns period=8.000ns})

解决方案

These failures cannot be ignored and will only occur when additional debug logic that uses a different clock domain are added into the MIG design or their user design. If no timing failures are seen, it is safe to continue debugging in hardware; but, if timing failures are seen, it is recommended to debug each memory interface individually and to use the same clk for each VIO/ILA instantiation. 

Revision History
06/19/2013 - Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 56387
日期 06/13/2013
状态 Active
Type 已知问题
器件
IP
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