Version Found: v2.0
Version Resolved: See (Xilinx Answer 54025)
All MIG QDRII+ 7 Series v2.0 designs infer a latch for signal init_rd_cmd_d_reg[0] inside phy_write_init_sm.v.
This should not affect hardware results as the timing for this path should have sufficient margin. However, the attached latch_timing_force_check.tcl script can be run on your design to check if timing is an issue. If so, the attached patch (AR57148.zip) can be applied to resolve the latch inference.
NOTE: Instructions for applying the patch for Vivado can be found in the readme.txt file which are located in the patch ZIP.
Revision History
08/16/2013 - Initial release
| 文件名 | 文件大小 | File Type |
|---|---|---|
| latch_timing_force_check.tcl | 333 Bytes | TCL |
| AR57148.zip | 17 KB | ZIP |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 54025 | MIG 7 Series - IP Release Notes and Known Issues for Vivado | N/A | N/A |
| AR# 57148 | |
|---|---|
| 日期 | 09/26/2013 |
| 状态 | Active |
| Type | 已知问题 |
| 器件 | |
| IP | |