AR# 57221

描述

Version Found: v2.0
Version Resolved: See (Xilinx Answer 54025)

MIG 7 Series DDR3 RDIMM designs have non-ideal settings for RC3/4/5 for DRAM loads of 8 or more. In some cases, this can cause ZQ calibration to fail and never enter write leveling.

解决方案

By default, RC3/4/5 are set for "Light Drive (4 or 5 DRAM Loads)" shown below:

  // RC3 timing control word. Setting the data to 0000
  localparam REG_RC3 = 8'b00000011;

  // RC4 timing control work. Setting the data to 0000 
  localparam REG_RC4 = 8'b00000100;

  // RC5 timing control work. Setting the data to 0000 
  localparam REG_RC5 = 8'b00000101;   

This is the correct setting for RDIMM's with 4 or 5 loads, but for Single Rank and Dual Rank DIMMs with 8 or more loads the drive strength should be increased.

To work around the issue, the following RTL changes can be made inside mig_7series_v2_0_ddr_phy_init.v:

  // RC3 timing control word. Setting the data to 0000
  localparam REG_RC3 = 8'b00010011;

  // RC4 timing control work. Setting the data to 0000 
  localparam REG_RC4 = 8'b00010100;

  // RC5 timing control work. Setting the data to 0000 
  localparam REG_RC5 = 8'b00010101;   

Revision History
08/28/2013 - Initial release

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