AR# 57758

描述

Version Found: MIG 7 Series v1.7a
Version Resolved: See (Xilinx Answer 54025)

If a MIG 7 Series input clock "sys_clk" is driven from a bank outside of the bank containing the memory interface PLL, the clock must route on the dedicated frequency backbone route to reduce jitter. There are four available frequency backbone routes. Three of these routes are used by PLL output blocks that drive the PHY hardblocks (i.e., Phasers). The remaining route should be used for "sys_clk" when it is driven from a separate bank. For more information, see (Xilinx Answer 40603). This routing is correct when MIG 7 Series is implemented in the ISE design tools. However, when the same design is implemented in the Vivado tool, the PLL to MMCM clock "pll_clk3" is placed on the fourth available backbone route preventing "sys_clk" from using the needed route. This occurs regardless of the backbone constraint applied to "sys_clk".

解决方案

To work around this issue and force the "sys_clk" onto backbone routing, add a BUFH to the PLL to MMCM clock "pll_clk3":

1. Open the "user_design/rtl/clocking/mig_7series_vx_x_infrastructure.v" module.
2. Add a wire called "pll_clk3_out"

   wire        pll_clk3_out;

3. Add a BUFH to the PLL to MMCM clock route "pll_clk3":

     BUFH u_bufh_pll_clk3
       (
        .O (pll_clk3),
        .I (pll_clk3_out)
        );

4. Connect the "pll_clk3_out" to the CLKOUT3 port of the plle2_i instance.
5. Re-implement the design.

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