Version Found: v2.0 Rev1
Version Resolved: See (Xilinx Answer 54025)
All MIG 7 Series VHDL designs fail simulations using VCS simulator due to a limitation with the way VCS maps VHDL generics to Verilog parameters.
This issue is scheduled to be fixed in VCS 2014.03 (Beta) and going forward.
Revision History
12/18/2013 - Initial release
| AR# 58634 | |
|---|---|
| 日期 | 12/06/2013 |
| 状态 | Active |
| Type | 已知问题 |
| 器件 | |
| IP | |