AR# 60927

描述

This Answer Record contains child answer recordscovering various aspects of the Vivado HLS design flow. 

The Answer Recordexplains where to find help with integrating the Vivado HLS output IP into therest of the system.

Note: This answer record is a part of the Xilinx SolutionCenter for Vivado HLS (Xilinx Answer 47428), which is available to address all questions related toVivado HLS. 

Whether you are starting a new design or troubleshooting a problem,use the Solution Center for Vivado Synthesis to guide you to the rightinformation. 

解决方案

Output Formats

The output from Vivado HLS can be used as an IPblock in either the Vivado Design suite, System Generator for DSP (Vivado andISE versions) or in Xilinx Platform Studio (XPS).

Only designs targeted forZynq and 7 Series devices can be used packaged the Vivado flows.

A fullexplanation of these IP packages can be found in the section "Exporting theRTL" in the VivadoDesign Suite User Guide High-Level Synthesis.

Although the RTL files are available in theVivado HLS project directory it is recommended to use one of the packaged IPformats.

If there is a requirement to use only the output RTL files, the filesfrom within the packaged IP directories should be used.

Do not use the HDLfiles in the project syn, impl/verilog or impl/vhdl folders, as these may nothave all required AXI buses interfaces.

Vivado and IP Integrator Flows

A Vivado HLS design can be used in the VivadoDesign Suite by creating IP for the IP Catalog. The Vivado QuickTake video PackagingVivado HLS IP for use from Vivado IP Catalog demonstrateshow IP can be exported to the Vivado IP catalog.

The tutorial Using HLS IP in IP Integrator inthe VivadoHLS Tutorialsshows how multiple Vivado HLS IP blocks can be created and assembled into afull system design using IP integrator.

An addition tutorial Using HLS IP in aZynq Processor Design shows not only how to connect up HLS IP in a Zynq designusing IP Integrator, but also how to integrate the IP with the software on theZynq CPU, process the entire design through the SDK software environment andrun the system on a ZC702 board.

The Application note AcceleratingOpenCV Applications with Zynq using Vivado HLS Video Libraries (XAPP1167, design files here) explains how a design with OpenCV functions isprocessed using Vivado and IP Integrator.

System Generator for DSP flows

A Vivado HLS design can be incorporated intoSystem Generator for DSP by creating IP for System Generator (Vivado or ISE).

The Vivado QuickTake videos GeneratingVivado HLS block for use in System Generator for DSP and UsingVivado HLS C/C++/System C block in System Generatordemonstrate how IP can be exported to System Generator and used.

The tutorial Using HLS IP in System Generatorfor DSP in the VivadoHLS Tutorialsshows how Vivado HLS IP blocks can be created and assembled into a SystemGenerator design.

TheApplication Notes Floating-PointPID Controller Design with Vivado HLS and System Generator for DSP (XAPP1163) and Implementing Carrier Phase Recovery Loop UsingVivado HLS (XAPP1173) both provide detailed application examples implementedusing Vivado HLS and System Generator for DSP.

Xilinx Platform Studio (XPS)Flows

The Vivado HLS output can be incorporated into adesign in Xilinx Platform Studio by System Generator for DSP by creating the IPin pcore format.

The Vivado QuickTake videos GeneratingVivado HLS Pcore for use in Xilinx Platform Studioand UsingVivado HLS C/C++/System C based Pcores in XPS demonstratehow IP can be exported to XPS and used in an ISE flow.

TheXPS and ISE flow is used in the Application Notes "Zynq-7000 SoC Accelerator for Floating-Point Matrix Multiplication usingVivado HLS" (XAPP1170) and "Zynq Sobel Filter Implementation Using Vivado HLS"(XAPP890) both provide detailed application examples implemented using VivadoHLS, XPS and ISE

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