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  4. AR# 62320: MIG 7 Series DDR2 - DQS overshoot on 200MHz design when CL=3

AR# 62320

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MIG 7 Series DDR2 - DQS overshoot on 200MHz design when CL=3

描述

 

Version Found: v2.1
Version Resolved: See (Xilinx Answer 54025)
The MIG 7 Series DDR2 design may experience DQS overshoot due to Taond violation when running at 200MHz and targeting a CAS Latency of 3 (CL=3).

 

 

解决方案


When 200MHz DDR2 with CL=3 is targeted, MIG PHY drives ODT later than the time required for the Taond specification so that DQS may overshoot on the first cycle of write operation.

This does not affect read or write operation or calibration, however may violate DQS DC specification.

To resolve the violation, set CAS latency = 4 in the core_name_mig.v file.

   ---CL                    : integer := 3;
       CL                    : integer := 4;

 

Revision History:

10/07/2014 - Initial Release

 

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 62320
日期 10/15/2014
状态 Active
Type 综合文章
器件
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