AR# 62583
|2014.x Vivado Simulator - xelab rangecheck may cause some IP cores to fail to elaborate by being too strict in handling VHDL null vectors
描述
When the rangecheck option is enabled for xelab in Vivado Simulator, a number of IP cores fail to elaborate with an error message similar to the following:
ERROR: [XSIM 43-3430] No value can belong to null range in file "d:/Work/Xilinx_Test_case/tst_top/tst_top.srcs/sources_1/ip/real_mult_18_18/mult_gen_v12_0/hdl/dsp.vhd" at line 1002
The use of a null vector is legal in VHDL, and is used in many IP cores to simplify highly generic code.
Questa does not report this error, even with the -rangecheck switch added to vcom.
Some of the affected IP cores:
- FFT
- FIR Compiler
- CIC Compiler
- DFT
- Multiplier
解决方案
The -rangecheck option enables run time value range check for VHDL.
You can disable this option to work around the issue.
The check for null vectors will be relaxed in Vivado 2015.1 and as a result the error will not occur in Vivado Simulator when -rangecheck is enabled.
链接问答记录
主要问答记录
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 58882 | Xilinx Simulation Solution Center - Design Assistant - Vivado Simulator - Behavioral Simulation | N/A | N/A |