2. 技术支持
  3. AR# 6289: 1.5i Virtex Map - Not all instances a timespec are being covered by the resulting .pcf file.
  4. AR# 62891: MIG 7 Series - DDR3 - 72-bit AXI4 interface generated with ECC disabled

AR# 62891

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MIG 7 Series - DDR3 - 72-bit AXI4 interface generated with ECC disabled

描述

Version Found: MIG v2.2
Version Resolved: See (Xilinx Answer 54025)

There is a known issue in MIG v2.2 where a 72-bit DDR3 AXI interface will be incorrectly generated with ECC disabled, even though ECC is shown enabled in the GUI.  

For 72-bit AXI interfaces, ECC is required as noted in (UG586):

eccmask.PNG




解决方案

To work around this issue, the following parameters will need to be modified in the <core_name>_mig.v module:
 

   parameter ECC                   = "ON",           // previously "OFF"
   parameter DATA_WIDTH            = 64,       // previously 72

Revision History:
01/26/2015 - Initial Release

AR# 62891
日期 03/05/2015
状态 Active
Type 已知问题
IP
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