AR# 63337
|VCS - Error-[EIRO] Illegal real operand rxtx_bitslice_002.vp, 1
描述
The following error message occurs in VCS in a simulation for BITSLICE_CONTROL.
Error-[EIRO] Illegal real operand<
/cadtools/Xilinx/Vivado/2014.2/data/secureip/rxtx_bitslice/rxtx_bitslice_002.vp, 1
I am using the library source files with compile time options by running the following commands.
=======================================================================================
vcs \
-l vcs.log \
+v2k \
-timescale=1ps/1ps \
-Xman=4 \
-y /cadtools/Xilinx/Vivado/2014.2/data/verilog/src/unisims \
-y /cadtools/Xilinx/Vivado/2014.2/data/verilog/src/unimacro \
-y /cadtools/Xilinx/Vivado/2014.2/data/verilog/src/retarget \
-f /cadtools/Xilinx/Vivado/2014.2/data/secureip/secureip_cell.list.f \
+incdir+/cadtools/Xilinx/Vivado/2014.2/data/verilog/src +libext+.v \
/cadtools/Xilinx/Vivado/2014.2/data/verilog/src/glbl.v \
+verilog2001ext+.vp \
-lca \
-f synth.tree \
=======================================================================================
解决方案
This is due to the SecureIP library source coding not strictly following the Verilog-2001 LRM standard.
Use either of the following methods to work around this issue:
- Add the -v2005 or -sverilog option to the VCS command.
- Compile the simulation libraries for VCS using compile_simlib and use pre-compiled libraries for simulation
This issue is planned to be completely fixed in the 2015.3 release.
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