General Description: Problems occur with a variable being used in the combination of the following items:
1. The variable is used as an index in the signal that is being operated on. 2. The variable is used as an index in a loop statement as the exponent. 3. The signal is passed to the function/procedure.
These points are illustrated in the following VHDL portions: . . . TYPE data_array IS ARRAY (integer range <>) OF std_logic_vector(7 DOWNTO 0);
Point 1: The variable "add_width" is used as an index in the signal "data".
SIGNAL data : data_array(0 to (2**add_width) );
procedure init_mem(signal memory_cell : inout data_array ) is begin
Point 2: The variable "add_width" is the upper bound in the loop as an exponent.
for i in 0 to (2**add_width) loop memory_cell(i) <= (others => '0'); end loop;
end init_mem; . . .
Point 3: The signal "data" is being passed to the procedure.