AR# 65468

描述

This answer record is a documentation map providing information about booting a Zynq UltraScale+ MPSoC device.

It links to documents which cover different modes and configurations for booting a Zynq UltraScale+ MPSoC device using your boot interface of choice.

Note: This answer record is part of Xilinx Zynq UltraScale+ MPSoC Solution Center (Xilinx Answer 64375).

The Xilinx Zynq UltraScale+ MPSoC Solution Center is available to address all questions related to Zynq UltraScale+ MPSoC.

Whether you are starting a new design or troubleshooting a problem, use the Zynq UltraScale+ MPSoC Solution Center to guide you to the right information.

解决方案

Boot Flows and Concepts (FSBL, image creation through BootGEN, multiboot, and fallback mechanisms) are described in 

• Chapters 11 and 12 of (UG1085)Zynq UltraScale+ MPSoC Technical Reference Manual
  https://www.xilinx.com/cgi-bin/docs/ndoc?t=user_guides;d=ug1085-zynq-ultrascale-trm.pdf
• Chapter 7, 8 and 15 of (UG1137) Zynq UltraScale+ MPSoC Software Developer Guide.
  https://www.xilinx.com/cgi-bin/docs/ndoc?t=user_guides;d=ug1137-zynq-ultrascale-mpsoc-swdev.pdf

Below are some more Xilinx Answers relevant for Boot and Configuration.

Primary Boot Devices

Zynq UltraScale+ MPSoC supports Quad-SPI, NAND, SD, and eMMC as primary boot interfaces.

(Xilinx Answer 65463) contains details about which memory vendors and devices families are tested and supported by Xilinx.

Boot Times for Zynq UltraScale+ MPSoC Devices

(Xilinx Answer 67475) Zynq UltraScale+ MPSoC - Boot Times Estimation