AR# 68594

描述

The Xilinx LogiCORE DSP48 Macro can be used to create RTL for the most commonly used DSP48 functionality.

For other use cases, examples and resources can be found throughout the DSP slice user guides.

Full list of applicable user guides:

• (UG579) - UltraScale Architecture DSP Slice User Guide
• (UG479) - 7 Series DSP48E1 Slice User Guide
  
• (UG369) - Virtex-6 FPGA DSP48E1 Slice User Guide
  
• (UG389) - Spartan-6 FPGA DSP48A1 Slice User Guide
  
• (UG193) - Virtex-5 FPGA XtremeDSP Design Considerations User Guide
  
• (UG073) - XtremeDSP for Virtex-4 FPGAs User Guide

解决方案

The DSP48E2 slice is the fifth generation of architecture. It built upon prior architecture's DSP slices by adding additional capabilities over time.

The various DSP slice user guides, (listed above), contain cumulative and supplemental material and references that can only be found in the previous versions of the DSP slice architecture documentation.

In particular, UG073, (Virtex4 - DSP48), and UG193, (Virtex5 - DSP48E), contain many useful RTL examples and references which will assist you when targeting the Xilinx DSP slices throughout all device families.

Please keep this in mind and familiarize yourself with all that these documents can offer.

Vivado IDE, Vivado HLS and System Generator for DSP also provide useful examples and templates within the tool, and are also a worthwhile resource which should be reviewed.