2. 技术支持
  3. AR# 7168:
  4. AR# 71680: VCU1525 - Unexpected behavior on QSFP0/QSFP1 and USER_SI570 clocks

AR# 71680

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VCU1525 - Unexpected behavior on QSFP0/QSFP1 and USER_SI570 clocks

描述

On some VCU1525 boards, it has been seen that QSFP0/QSFP1 clocks come up at 161MHz and not the documented 156.25MHz clock.

In addition, the USER_SI570 clock is not toggling.

解决方案

In order to use the 156.25MHz QSFP0/QSFP1 rate, the user needs to drive the two QSFP#_FS[1:0] pins appropriately, and then issue a QSFP0_REFCLK_RESET.

Alternatively, the MGT_SI570_CLOCK0 pin (connected to FPGA PIN M11 on MGTREFCLK0 in Quad 231) can be used. 

This powers on to 156.25MHz and does not require any GPIO to configure its rate.

Instead of using the USER_SI570 clock, the 300MHz clock can be fed to an MMCM, or MGT_SI570_CLOCK0 can also be fed from IBUFDS_GT -> BUFG.





链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69844 Virtex UltraScale+ FPGA VCU1525 Data Center Acceleration Development Board - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 71680
日期 11/01/2018
状态 Active
Type 综合文章
Boards & Kits
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