2. 技术支持
  3. AR# 7262: FPGA Express: Is there an option to disable carry logic?
  4. AR# 72621: 2019.1.2 Vivado - Vivado 2019.1 Update 2 (2019.1.2) Release Notes and Known Issues

AR# 72621

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2019.1.2 Vivado - Vivado 2019.1 Update 2 (2019.1.2) Release Notes and Known Issues

描述

This answer record serves as the Vivado 2019.1 Tool Update 2 (2019.1.2) Release Notes, and contains links to information about what is included in the update.

解决方案

Vivado Design Suite 2019.1 Update 2 is now available with support for the following:

  • Production devices enabled:
    • Virtex UltraScale+ HBM Devices (-1, -2, -2L, -3): XCVU45P, XCVU47P
    • Virtex UltraScale+ 58G Devices (-1E, -1I, -2E, -2I): XCVU27P, XCVU29P

For customers using these devices, Xilinx recommends installing Vivado 2019.1.2.

For other devices, please continue to use Vivado 2019.1.

Downloading and installing the Vivado 2019.1 Update 2 (2019.1.2)

  • The update is available at: https://www.xilinx.com/download
  • It must be applied to an existing installation of 2019.1 (SW Build 2552052), and will bring the Vivado version to 2019.1.2.


Known Issues specific to Vivado 2019.1 update 2 (2019.1.2)

There are currently no known issues associated with this release.

  • For Vivado 2019.1 known issues see: (Xilinx Answer 72162)
  • For known issues related to a specific IP, please search the support site for "Known Issues" and the IP name.

AR# 72621
日期 08/14/2019
状态 Active
Type 综合文章
Tools
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