The Xilinx University Program (XUP) enables academics to introduce and use Xilinx technologies in their curriculum and research. XUP collaborates with application expert academics to develop and deliver top-quality teaching materials. XUP also develops in-house workshop materials, teaching users how to use the tools and technologies in the most efficient ways. These workshop materials are accessible to academics to use in classes in their original forms and/or extend with additional material. XUP also gets actively involved in research projects where Xilinx FPGA technologies are utilized.
XUP has developed number of workshops using Vivado Design suite. These workshops are typically two days long. All workshop materials are in English and consist of presentation slides and lab documents.
Professors can freely re-use the presentation material in their classroom for teaching purpose. There is no restriction to add, modify or delete the slides giving professors complete control and flexibility to incorporate the material according to the course objectives.
The lab source files are available and can be given to the students to carry out the labs. Lab solutions are only available to the professors. They should not be given to students.
| Tile | Level | Boards | Versions |
| FPGA Design Flow using Vivado | Introductory | ZedBoard, ZYBO, Nexys4/DDR, NexysVideo, Basys3, PYNQ-Z1, PYNQ-Z2 | 2018x, 2016x, 2015x |
| Embedded System Design Flow on Zynq | Introductory | ZedBoard, ZYBO, PYNQ-Z1, PYNQ-Z2 | 2018x, 2015x, 2014x |
| High-Level Synthesis Flow on Zynq | Introductory | ZedBoard, ZYBO, PYNQ-Z1, PYNQ-Z2 | 2018x, 2017x, 2016x |
| System Design on Zynq using SDSoC | Introductory | ZedBoard, ZYBO, PYNQ-Z1, PYNQ-Z2 | 2018x, 2017x, 2016x |
| Advanced Embedded System Design on Zynq | Intermediate | ZedBoard, ZYBO, PYNQ-Z1, PYNQ-Z2 | 2018x, 2017x, 2016x |
| Embedded Linux on Zynq (Archived) | Intermediate | ZedBoard, ZYBO | 2015x, 2014x, 2013x |
| System Design Flow on Zynq (Archived) | Intermediate | ZedBoard, ZYBO | 2015x, 2014x, 2013x |
| Partial Reconfiguration Flow on Zynq | Intermediate | ZedBoard, ZYBO | 2016x, 2015x, 2014x |
| Title | Level | Boards | Versions |
| FPGA Design Flow | Introductory | Atlys, Nexys3, XUPV5, Genesys, S3E Kit | 13.x, 12.x |
| DSP Design Flow | Introductory | Atlys, XUPV5, S3E Kit | 14.x, 13.x, 12.x |
| Embedded System Design Flow on Zynq | Introductory | ZedBoard | 14.2 |
| Embedded System Design Flow on MicroBlaze | Introductory | Atlys, Nexys3, XUPV5, Genesys, S3E Kit | 14.2, 13.x, 12.x |
| High-Level Synthesis Flow on Zynq | Introductory | ZedBoard | 14.2 |
| High-Level Synthesis Flow on MicroBlaze | Introductory | Atlys | 14.x, 13.x |
| Advanced Embedded System Design on Zynq | Intermediate | ZedBoard | 14.4 |
| DSP Primer | Intermediate | ZedBoard, Atlys | 14.4 |
| Embedded Linux on MicroBlaze | Intermediate | Atlys | 14.2 |
| Partial Reconfiguration Flow | Intermediate | ML605, XUPV5, Genesys | 14.2, 13.x, 12.x |
Vivado-Based Digital Design using IPI
Vivado-Based Digital Design using HDL
ISE-Based Digital Design using HDL
Coming Soon!
XUP Supported Boards
XUP supports an expanded range of hardware development systems using Xilinx technology to complement the classroom theoretical concepts with hands-on learning in the laboratory.
Vivado Design Suite: System Edition
An integrated software solution supporting the combined methodologies of logic/connectivity, embedded, and DSP design. Available for faculty and researchers.
ISE Design Suite: System Edition
An integrated software solution supporting the combined methodologies of logic/connectivity, embedded, and DSP design. Available for faculty and researchers.
Partial Reconfiguration
Partial Reconfiguration is available as a product within ISE Design Suite, however, requires special licensing to enable this feature. This feature is available to professors and researchers who meet certain criteria. Learn more on requirements and procedure in obtaining license>>
High-Level Synthesis
High-Level Synthesis capability is provided through Vivado High-Level Synthesis. This feature is available as part of the Vivado Design Suite System Edition allowing to target 7-Series and Zynq programmable families. Minimum of ISE Design Suite and a separate feature are required for a complete design flow targeting V6, S6, V5, V4, S3x and V2P. Professors and researchers who want to use this feature targeting the V6, S6, V5, V4, S3x, and V2P families may fill out the donation request form by clicking on the appropriate link in the Quick Links section on the right.
SDAccel Development Environment
The SDAccel™ development environment for OpenCL™, C, and C++, enables up to 25X better performance/watt for data center application acceleration leveraging FPGAs. SDAccel, member of the SDx™ family, combines the industry’s first architecturally optimizing compiler supporting any combination of OpenCL, C, and C++ kernels, along with libraries, development boards and the first complete CPU/GPU like development and run-time experience for FPGAs.
SDSoC Development Environment
The SDSoC™ development environment provides a familiar embedded C/C++ application development experience including an easy to use Eclipse IDE and a comprehensive design environment for heterogeneous Zynq® SoC and MPSoC deployment. Complete with the industry's first C/C++ full-system optimizing compiler, SDSoC delivers system level profiling, automated software acceleration in programmable logic, automated system connectivity generation, and libraries to speed programming. It also enables end user and third party platform developers to rapidly define, integrate, and verify system level solutions and enable their end customers with a customized programming environment.
Access IP
A robust catalog of base-level cores to address the general needs of FPGA designers as well as powerful domain and market specific cores to address DSP, embedded, and connectivity designs.
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Technical Documentation
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Service Portal
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Donation Program
XUP supports faculty through software donation of Vivado Design Suite: System Edition to start a new or enhance an existing course or research project.
General XUP Program information
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Software Licensing
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