At OFC 2017, Xilinx will be showcasing next-generation data center interconnect solutions, IEEE compliant 400GE in a live multi-vendor environment, and our latest transceiver and Flex-E optical solutions performing at the highest levels of bandwidth required within the industry.
Join us for a look at how our solutions address the high density, scalability and flexibility requirements for optical transport, carrier Ethernet and data center interconnect applications.
During Exhibit Hours | Xilinx Booth
The following demos will be featured from Xilinx and its ecosystem throughout the show.
Industry First 400GE Multi-Vendor Network
This demo features the world’s first standards-based 400GE MAC and PCS IP in a Xilinx Virtex® UltraScale+™ VU9P FPGA. Showcasing the emerging 400GE standard interoperability between multiple vendors, the demo illustrates the Xilinx 400G solution connecting to a 400GE CFP8 400GBASE-LR8 module which in turn connects to a 3rd party test set in the Ethernet Alliance booth.
FlexE for DCI Transport
Demonstrating FlexE, this demo illustrates channelization functions and demonstrates how multiple clients can be transported using FlexE. It will also highlight the ability of FlexE to carry larger data pipes and match them to transport links for optimal utilization of the link budget.
Optical Technology Abstraction in DCI Transport
With the emergence of differing optical technologies (DSPs, PAM4, Coherent, Extended Reach LR) customers must abstract such technologies from a system and software perspective. This demo illustrates how Xilinx FPGAs provide the required abstraction from differing technology integration by different manufacturers and enable designers to choose or mix optical technologies on a single platform.
Automation and Security Functions for DCI Solutions
This demonstration shows how LLDP packets can be snooped on transport line cards to allow a SDN controller to build a network topology for automation integral to data center networks. It also shows the use of IEEE compliant MACSec to encrypt and authenticate the link for security.
56Gb/s PAM-4 Transceiver Performance over Backplane
This demonstration showcases Xilinx’s 56G PAM-4 Transceiver test chip in 16nm FinFET.
During Exhibit Hours | Xilinx Booth
Xilinx booth will feature various boards from our ecosystem partners.
Booth # 1809
Los Angeles Convention Center
Los Angeles, CA
Tuesday, March 21
10:00 AM – 5:00 PM
Wednesday, March 22
10:00 AM – 5:00 PM
Thursday, March 23
10:00 AM – 4:00 PM
Xilinx Conference Participation
Xilinx experts will be participating in the following product showcases.
Wednesday, March 22
1:30 PM – 1:50 PM
400GE from Hype to Reality
400GE is the new Ethernet speed on the block set to finally become a reality in 2017 after much hype, discussion and standardization effort. This presentation will explore the realities of the 400GE ecosystems, deployment models and why the time for 400GE has arrived.
Presenters: Mark Gustlin, Principal System Architect, Xilinx | Brad Booth, Principal Engineer, Microsoft | Dave Ofelt, Distinguished Engineer, Juniper
Wednesday, March 22
2:00 PM – 2:20 PM
P4 Programmable Packet Processing for NFV/SDN
This panel session discusses the adoption of P4, the emergent high-level language for packet processing, and early implementations of P4 for FPGA and ASIC targets.
Moderator: Gordon Brebner, Distinguished Engineer, Xilinx
Panelists: Ed Doe, VP of Product and Strategy, Barefoot Networks | Denis Matousek, Senior Product Manager, Netcope Technologies | Michael Miller, VP of Technology Innovation and System Application, MoSyS