H16750S - 16750 UART with FIFOs and Synchronous CPU Interface

  • 产品编号: H16750S
  • 供应商: CAST, Inc.
  • Certified Partner

产品描述

The H16750S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16750 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices. The H16750S can be run in either 16450-compatible character mode or FIFO mode, where an internal FIFO relieves the CPU of excessive software overhead..


主要特性与优势

  • Adds or strips standard asynchronous communication bits (start, stop and parity) to or from the serial data.
  • Capable of running all existing 16450 and 16550a software.
  • Fully Synchronous design. All inputs and outputs are based on rising edge of clock.
  • Fully programmable serial interface characteristics: 5, 6, 7, or 8 bit characters. Even, odd, or no-parity bit generation and detection. 1, 1½, or 2 stop bit generation. Baud generation.
  • Programmable baud generator divides any input clock by 1 to (2**16 - 1) and generates the 16 x clock.
  • Independently controlled transmit, receive, line status and data set interrupts.
  • Modem control functions (CTSn, RTSn, DSRn, DTRn, RIn, and DCDn).
  • Programmable Auto-CTSn and Auto-RTSn. In Auto-CTSn mode, CTSn controls the transmitter. In Auto-RTSn mode, the receiver FIFO contents and threshold control RTSn .
  • In FIFO mode, transmitter and receiver are each buffered with up to 256 byte FIFO’s to reduce the number of interrupts presented to the CPU. Available with FIFO sizes of 8, 16, 32, 64, 128 or 256 bytes.

特色技术文档

器件实现矩阵

面向此核实现范例的器件使用矩阵。联系供应商了解更多信息。

系列 器件 速度等级 工具版本 硬件验证? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-7 Family XC7K480T -3 Vivado 2019.1 N 194 582 0 0 0 0 609
ARTIX-7 Family XC7A200T -3 Vivado 2019.1 N 195 575 0 0 0 0 435
VIRTEX-7X Family XC7VX330T -3 Vivado 2019.1 N 198 580 0 0 0 0 598
VIRTEX-U Family XCVU095 -3 Vivado 2019.1 N 114 547 0 0 0 0 700
KINTEX-U Family XCKU035 -3 Vivado 2019.1 N 114 545 0 0 0 0 700

IP 质量指标

综合信息

数据创建日期 Mar 09, 2022
当前 IP 修订号 1V24N00S00
当前修订日期已发布 Feb 22, 2016
第一版发布日期 Jun 20, 2002

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 22
可否提供参考? N

交付内容

可供购买的 IP 格式 Netlist, Source Code
源代码格式 VHDL, Verilog
是否包含高级模型? N
提供集成测试台 Y
集成测试台格式 VHDL
是否提供代码覆盖率报告? Y
是否提供功能覆盖率报告? N
是否提供 UCF? UCF
商业评估板是否可用? N
是否提供软件驱动程序? N
驱动程序的操作系统支持 N/A

实现方案

代码是否针对 Xilinx 进行优化? N
标准 FPGA 优化技术 Inference
定制 FPGA 优化技术 BRAMs
所支持的综合软件工具及版本 Mentor Precision; Synplicity Synplify; Vivado Synthesis
是否执行静态时序分析? N
是否包含 IP-XACT 元数据? N

验证

是否有可用的文档验证计划? No
测试方法 Directed Testing
断言 N
收集的覆盖指标 Code
是否执行时序验证? Y
可用的时序验证报告 N
所支持的仿真器 Mentor ModelSIM; Mentor Questa; Synopsys VCS; Cadence NC-Sim

硬件验证

在 FPGA 上进行验证 N
所使用的硬件验证平台 None
已通过的行业标准合规测试 N
特定的合规测试 N/A