Hardware Evaluation Time Out Period * : ~ 8 hrs
| LogiCORE™ | 版本 | AXI4 支持 | 软件支持 | 支持的器件系列 |
| 40G/50G Ethernet Subsystem |
v3.2 | AXI4-Stream | Vivado® 2021.2 | Versal™ ACAP Kintex® UltraScale+™ Virtex® UltraScale+ Zynq® UltraScale+ MPSoC Zynq UltraScale+ RFSoC Kintex Ultrascale™ Virtex UltraScale |
Download the required software from the Xilinx.com Downloads page. For information on New Features, Known Issues, and Patches please refer to the Licensing Solution Center.
* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.
The IP cores in this table will be fully functional in the programmed device for certain amount of time. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again.