AR# 14887: Virtex-II/-II Pro/-4/-5/-6/-7, Configuration - Dual-purpose configuration pins do not function properly when they are set to a DCI standard
AR# 14887
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Virtex-II/-II Pro/-4/-5/-6/-7, Configuration - Dual-purpose configuration pins do not function properly when they are set to a DCI standard
描述
Some dual purpose pins (D0-D7, D0-D31 (in Virtex-4/-5/-6/-7 devices), INIT, ALT_VRP, ALT_VRN, and DOUT) can also be used as regular I/Os after configuration. However, if I use the "FreezeDCI:Yes" option and set those pins to DCI I/O standards, they do not function properly.
I observe the same behavior when setting "DCIUpdateMode:Quiet" in Virtex-II Pro/-4/-5/-6/-7 devices. What causes this problem?
解决方案
These I/Os do not function properly if the following three conditions are true:
The D0-D7, D0-D31 in V-4/-5/-6, INIT, ALT_VRP, ALT_VRN, or DOUT pins are used as I/O after configuration.
One or more of those pins is a DCI input or output.
The "FreezeDCI" option is set to "Yes" or "DCIUpdateMode" option is set to "Quiet".
For an output, the I/O is put into a tri-state condition or does not have the correct termination. For an input, the I/O does not have the correct termination.
The issue is that during configuration, the Termination settings are not appropriately sent to the dual purpose pins since they are in configuration mode. Once they switch to regular I/O mode, if the DCI information is not set to continuously update the termination structure, the I/Os will not have termination leg information.
To work around this issue, you can set the DCI state machine to update continuously (DCIFreeze:NO or DCIUpdateMode:Quiet). Alternately, in Virtex-4/-5/-6, you can instantiate the DCIRESET block and manually assert a DCI update after configuration to have the termination set appropriately.
NOTES:
This problem does not affect the RDWR_B and CS_B signals, which are also dual-purpose configuration pins.
FreezeDCI is available in Virtex-IIdevices.
For Virtex-II Pro/-5/-6/-7 devices, DCIUpdateMode should be set to "Continuous".
In devices that support DCI_Cascade, pins in slave banks will be affected.