AR# 23985

描述

This Answer Record contains Release Note information for LogiCORE Block Plus Endpoint for PCI Express v1.1.

解决方案

Initial Release of LogiCORE Block Plus Endpoint for PCI Express v1.1

A CORE Generator update (8.2i IP Update 2 LXT Supplement) is available containing the initial release of the PCI Express Endpoint Block Plus LogiCORE v1.1. This must be downloaded and installed on top of your current 8.2i sp3 IP Update 2 installation. For general information about this update, please see (Xilinx Answer 24008). This update can be found at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp.

General Information

The Virtex-5 LXT device contains a dedicated PCI Express Endpoint Block. Xilinx recommends the use of one of the two available wrappers produced by CORE Generator when targeting the PCI Express Endpoint Block in Virtex-5 LXT. Two wrappers are available, each with its own unique features. For more information on the wrappers, please refer to:

http://www.xilinx.com/ipcenter/V5LXT_pcie_ep_sel_guide/index.htm

Known Issues

--When using a -1 speedgrade, timing failures might occur when implementing a x4 or x8 core design using 250 MHz for the transaction interface frequency or on the 250 MHz interface between the PCI Express block and the GTP transceivers. Note that the transaction interface clock domain is different from the system reference clock input. Regardless of the system reference clock input frequency (either 100 MHz or 250 MHz), the transaction interface frequency can be either 125 MHz or 250 MHz. For more information on selecting the transaction interface clock frequency, please refer to the PCI Express Endpoint Block Plus User's Guide or pcie_blk_plus_ug341.pdf available in the doc directory with the generated core. This issue will be fixed with the ISE 9.1i IP Update 1 core release planned for February 2007.

--Designs implementing BARs of type IO space will fail to simulate correctly because of a problem when NETGEN produces the simulation model of the core. This issue will be fixed in the 9.1i software release. This is a problem in simulation only and does not affect hardware operation.

--Please see (Xilinx Answer 24174) regarding information if you receive an error stating "ERROR:coreutil - Failure to generate output products" in CORE Generator.