AR# 30980

描述

This Release Notes and Known Issues Answer Record is for the Endpoint Block Plus Wrapper v1.8, released in ISE 10.1 IP Update 2 (IP_10.1.2), and contains the following information:

- General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:

http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf

解决方案

General Information

The LogiCORE Endpoint Block Plus for PCI Express requires a license to generate and implement the core. There is no charge for this license.

To obtain the license, visit the product lounge at:

http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?iLanguageID=1&sGlobalNavPick=&sSecondaryNavPick=&key=V5_PCI_Express_Block_Plus

New Features

- ISE 10.1 SP2 design tools support

- Added FAST Functional Simulation model support for GTP

- Added a Dual Core Example Design for Virtex-5 FX70T

Resolved Issues

CR 454139: MTI Secure IP related Issue

Removed Xilinx_lib_mti.f from MTI flow as compxlib should account for compilation of unisim models for GT11 and SecureIP models for GTP/GTX and PCIe Hard Block.

CR 442552: Dual Core Example Design

Added a Dual Core Example Design to be generated for Virtex-5 FX70T only.

CR 458537: Tx Transmission Issues

Implemented a work-around for the "Tx Transmission Issues due to lack of Data Credits" Virtex-5 PCIe Block Restriction.

CR 469909: Update GTP wrapper

Update the GTP wrapper to remove TXBUFFERBYPASS mode.

CR 466714: Transfer of CORE Generator speedgrade option into delivered UCF

Issue resolved where the CORE Generator speedgrade selected was not being passed into the UCF.

CR 466393: PIO Example Design State Transition

Issue resolved where the PIO Example Design had an incorrect state transition in the TX state machine.

CR 467806: Added Fast Functional Simulation model support for GTP

Added Fast Functional Simulation model support for GTP.

CR 472100: Updated OOB_THRESHOLD values for GTX

Updated the OOB_THRESHOLD values for GTX as per latest recommendation for PCI Express Specification Compliance.

CR 472721: 8 lane product support for Virtex-5 LX30T

Issue resolved where support for the 8 lane product on Virtex-5 LX30T had been removed.

CR 472588: Receipt of Back to Back ACKs causing TX Lockup - 8 lane only

Issue resolved where receipt of Back-to-Back ACK DLLPs could cause the Integrated Hard Block to Lock-up in the transmit direction. This issue only affected the 8 lane product.

Known Issues

There are three main components to the Endpoint Block Plus Wrapper for PCI Express:

- Virtex-5 FPGA Integrated Block for PCI Express

- Virtex-5 FPGA GTP/GTX Transceivers

- Block Plus Wrapper FPGA fabric logic

There are known issues and restrictions for each of these components, as described below:

Virtex-5 FPGA Integrated Block for PCI Express Known Restrictions

Refer to the "Virtex-5 Integrated Endpoint Block for PCI Express Designs User Guide"

for a list of Known Restrictions for the Integrated Block. This information is included in Chapter 4, in the "Known Restrictions" section. This guide is located at:

http://www.xilinx.com/support/documentation/user_guides/ug197.pdf

Virtex-5 FPGA GTP/GTX Transceivers

See (Xilinx Answer 31207).

Block Plus Wrapper FPGA fabric logic

(Xilinx Answer 31209) - Endpoint Block Plus Wrapper v1.8 for PCI Express - FXT based core uses TXBUFFER Bypass for GTX

(Xilinx Answer 31166) - Endpoint Block Plus Wrapper v1.8 for PCI Express - Set Slot Clock Configuration bit in Link Status register not getting set

(Xilinx Answer 31203) - Endpoint Block Plus Wrapper v1.8 for PCI Express - Endpoint Block Plus Wrapper for PCI Express v1.8 - Unable to customize BAR 3 fields within Core generator GUI.

(Xilinx Answer 31161) - Endpoint Block Plus Wrapper v1.8 for PCI Express - TRN_TSRC_RDY_N Deassertion Causing Continuous TRN_TDST_RDY_N Deassertions

(Xilinx Answer 31164) - Endpoint Block Plus Wrapper v1.8 for PCI Express - MPS of 128 or 256 bytes causing Received TLP bit errors due to Expansion ROM work-around

(Xilinx Answer 31165) - Endpoint Block Plus Wrapper v1.8, Endpoint PIPE v1.7, and Endpoint Soft-IP v3.6 for PCI Express - Downstream Port Model Testbench uses the word "type" causing problems with System Verilog

(Xilinx Answer 31210) - Endpoint Block Plus Wrapper for PCI Express v1.8 - Interrupt Status bit not set when generating Legacy Interrupt

(Xilinx Answer 31292) - Endpoint Block Plus Wrapper v1.8 for PCI Express - Transmit (TX) Lockup Due to Link Partner Advertising Infinite Posted Data Credits

(Xilinx Answer 31376) - Endpoint Block Plus Wrapper v1.8 for PCI Express - Transmit Lockup on First Completion Transmitted after Link Up

(Xilinx Answer 31460) - Endpoint Block Plus Wrapper v1.8 for PCI Express - CORE Generator Customization GUI Page 7 TXPREEMPHASIS Wrong for FXT

Revision History

08/15/2008 - Added 31460

07/21/2008 - Added 31376

07/14/2008 - Changed format of title

07/11/2008 - Added 31292

06/23/2008 - Corrected GTP/GTX Known Issue reference to (Xilinx Answer 31207) instead of 30632.

06/18/2008 - Initial Release