AR# 32996: Virtex-5/Virtex-6 GTP/GTX and Spartan-6 GTP Transceiver Wizard - Timing not met on implemented example design
AR# 32996
|
Virtex-5/Virtex-6 GTP/GTX and Spartan-6 GTP Transceiver Wizard - Timing not met on implemented example design
描述
When RXRECCLK is used to generate RXUSRCLK, it is possible that timing will not be met upon implementation. This Answer Record discusses the issue and how to work around it.
解决方案
When RXRECCLK is used to generate RXUSRCLK or multiple reference clocks are used, it is possible for the clock supplying the automatically generated ChipScope ILA Core to fail timing. Currently, the only method for working around this problem is to remove the automatically generated ChipScope cores. The simplest way to do this is to set the EXAMPLE_USE_CHIPSCOPE parameter to 0.